First-in first-out (FIFO) memories receive data synchronized with a write clock and output data synchronized with a read clock, the read clock and write clock being asynchronous with each other. The FIFO memory has a plurality of serially arranged storage cells which are sequentially written into and read from. The term "write pointer" is used to indicate the storage cell presently being written into and the term "read pointer" is used to indicate the storage cell presently being read from.
In order for the FIFO memory to operate without creating bit errors, each storage cell must be alternately written into and then read from, i.e., no storage cell is written into twice in succession without an intermediate read operation and no storage cell is read from twice in succession without an intermediate write operation. In order to prevent this type of bit error from occurring, FIFO memories typically detect if the write pointer and the read pointer are separated by a predetermined number of memory cells and provide status flags at output terminals which indicate whether the memory is full or empty. By definition, the write pointer will always lead the read pointer since the data cannot be read until it is written.
In addition, because packets of data, for example, 1 byte of data, must often be transferred as a group, it is sometimes necessary to provide almost full and almost empty flags which detect, in this example, if the memory is 8 bits from full or 8 bits from empty. A half status flag which indicates if half or more of the memory has been written into without a succeeding read operation may also be desirable.
Because the read and write clocks which control the FIFO are totally asynchronous, the proper detection of the state of the memory can be very difficult. Due to its asynchronous nature, the FIFO memory is prone to arbitration problems as the clocks become skewed and operate at different frequencies.